Primary ESD Protection

ESD protections from simple to complicated

Zener Diode Protection

The most simple structure is the substrate zener diode. It's break down voltage mainly depends on the substrate doping and tracks the drain-bulk break down of the low voltage NMOS. In other words: When the substrate zener diode breaks the low voltage NMOS is already destroyed.

Fig. 1: Substrate zener diode

Fig. 2: ESD protection with zener diode.

The substrate zener diode will acceptably well protect NMOS transistors with low doped drain extension. If it is used to protect low voltage NMOS transistors the spacing between the n-plus (cathode) and the p-plus (substrate contact) must be reduced such that the depletion area reches the p-plus region before the NMOS transistors break. In extreme cases n-plus and p-plus can touch to obtain a break down voltage of only a few volt.
The following plot shows the voltages V2 and V3 of such a protection.

Fig. 3: Simulation of a zener protection

Estimation of the Size needed

Once the ideal clamping voltage and the quivalent series resistance of the zener diode is known the dissipated energy can be calculated:


Example according to MIL883-STD, 4kV:
R=1.5k
C=150pF
Vz=5V
Rz=2 Ohm
4kV ESD pulse
leads to  Ip= 4kV/1.5K = 2.67A, E=4.61uJ.

Due to the short duration of the pulse the heat can not flow further away from the junction than about 2um. The silicon should not heat up more than to about 1500°C because above 1600°C silicon begins to melt. The mass of the silicon needed can be calculated using the thermal capacity of silicon



With Cth = 0.7Ws/gK

So we need a mass of

m = 4.61uJ/(0.7Ws/gK * 1500K) = 0.0044ug

The specific weight of silicon is 2.33g/cm³. This leads to a required volume of:

V = W*2um*4um = m/2.33g/cm³

Solving for W we end up with about

W=235um

Due to the fact that we have to keep certain minimum spacings the area of a 4kV HMB zener protection becomes about

A=(W+10um)*15um=3675um²

Snap Back Protections

The simple zener protection has two drawbacks:
1. It requires a fairly large size
2. The characteristic is soft. This leeds to a poor protection performance.

The Idea behind snap back protections is to lower the clamping voltage once the structure is triggered. This lowers the energy to be absorbed and thus reduces the size needed. Let us assume the structure snaps back to a hold voltage of 2V in stead of a current dependent clamping voltage arround 8V as in the upper example. The calculation of the energy remains basically the same as before except that we have to replace the zener voltage Vz by the hold voltage Vh of now 2V.
The energy to be absorbd reduces to now:

E = 2.81uJ

The thermal mass becomes:

m = 0.0027ug

And the required width of the structure drop to:

W = 143um

leading to an area of now:

A=(143um+10um)*15um=2295um³

A saving of about 30%.
But there is a price to pay. The snap back structure relies on the voltage at the pin to be protected to drop below the snap back voltage or the current to drop below the hold current. If there is a combination of a DC voltage above the snap back voltage and a superimposed ESD pulse the snap back structure will be destroyed by the resulting DC current after the pulse.


Fig. 4: Characteristic of a snap back protection

An ESD pulse will turn on the structure reaching Vtrip. Further increase of the current will take the structure from Vtrip to the part of the characteristic where the voltage jumps back to Vhold. Due to the high current of the ESD pulse the ESD protection will operate on the dashed part of the characteristic. Operation in this area only is allowed for a very limited time. DC operation in the dashed region is not allowed.

If a DC source is connected with open source voltage VDC two cases have to be distinguished:
Case 1: The DC source has a high impedance (solid load line). The intersection between the solid load line and the characteristic of the ESD protection is in the solid part of the characteristic and will not destroy the structure.
Case 2: The DC source is low resistive (dashed load line). Before the ESD pulse the structure operates at the intersection between the dashed load line and the solid drawn part of the characteristic (allowed OP). After the ESD pulse has triggered the structure the operating point will jump to the intersection of the dashed load line and the dashed part of the protection characteristic. The structure will not turn off anymore. Best case the input signal at the pin is unintentionally clamped. Worst case the DC power dissipation at the forbidden operating point is so high that the structure gets destroyed.

Fatal Combination of a Capacitor and a Snap Back Structure

The following combination sould be avoided:


Fig. 5: Fatal combination of snap back structure and external capacitor

Let us assume C is charged to a voltage between Vhold and Vtrip of fig. 4. An ESD pulse (generated closing SW) will create a spike at the pins of the IC. Blocking capacitor C can not absorbe the spike because of it's parasitic pin inductances. Therefore the ESD protection will trigger. Once triggered the protection snaps back to Vhold discharging the external capacitor C.


Example:
The ESD protection is designed to absorb 3uJ at a hold voltage of 2V. This is an appropriate design for 4kV MIL-STD883D. Assuming C is charged to 5V and has a value of 10uF the energy stored in the capacitor is:

E1 = 0.5*C*V² = 0.5*10uF*25V² = 125uJ

After the discharge the energy remaining is:

Typical Implementations of Snap Back Structures

Open Base NPN

Most common snap back structure is an NPN transistor with open base. This structure is typical for a standard bipolar process. Compared to the standard transistor the spacing between collector and base can be reduced to achieve a lower break down voltage than that of the element to be protected.

Fig. 6: Open base NPN transistor (contact opening shown, metal not shown)

The design shown above requires two metal layers to connect emitter and collectors sufficiently low resistive. In Technologies with only single metal (or when metal 2 is used for someting else) only one side of the structure (only one collector) is implemented.

Grounded Gate NMOS

A grounded gate NMOS is a typical structure in CMOS technologies. I consists of several parts:
- An NMOS transistor with a miller capacity between the gate and the drain.
- A bipolar NPN transistor with the source of the NMOS acting as emitter and the drain acting as collector
- A base resistance of the NPN created by the placement of the bulk contact od the NMOS transistor
- A resistor between the gate of the NMOS and the source.


Fig. 7: grounded gate NMOS

At an ESD event the drain gate capacity turns on the NMOS transistor. At the same time the drain-bulk capacity raises the bulk voltage of the NMOS transistor thus lowerings it's threshold.
When the bulk of the NMOS transistor reaches VBE of the bipolar transistor this transistor turns on additionally.
For negative pulses an anti parallel diode ca be used. This can be implemented in a simple way placing a second bulk contact right of the drain (not shown in the figure above). Reducing the bulk resistance moving the bulk contakt closer to the source is a second alternative. In this case the bipolar transistor takes over a smaller fraction of the total current and the NMOS transistor must be scaled larger.
The same structure can be built for reverse polarity with a PMOS transistor and a PNP bipolar transistor. This structure however is much less efficient due to the lower mobility of holes in stead of electrons.

Thyristors

This is the brute force method for very high energy pulses. The basic idea is to create a structure with extremely low hold voltage to minimize the energy to be dissipated in the structure. This structure often is used when ESD pulse of more than 10kV must be survived. Unfortunatelly thyristors do not perform well in systems with big blocking capacitors belonging to the application (see the 'fatal combination' described above).
Classically thyristors were composed of bipolar components. Of course MOS implementations are possible too but require more die area.

Fig. 8: Thyristor in CMOS technology

THe NPN tranistor Q1 is a lateral transistor with the N+ region left acting as emitter nd with the nwell region acting as collector. The PNP transistor Q2 is a vertical component with the nwell acting as base, the right P+ area acting as emitter and the substrate acting as collector. The two resistors R1 and R2 are the path resistances in the substrate (R1) and the nwell (R1). The hold current calculates as:

I_h = Vbe/R

with R being the lower resistive one of the two R1, and R2.
The trigger voltage is mainly a function of the break down voltage between the nwell and the substrate. This is represented by the dashed diode D. To lower the break down voltage the N+ contact connecting the base of Q2 can be moved closer to the edge of the nwell than the regular design rules of the process recommend. In some cases the N+ region overlaps the nwell to create an aprupt junction.
To make the structure respond faster the nwell to substrate capacity can be increased intentionally.

The structures shown only illustrate basic ideas of ESD rail clamps but of course they are far from a complete picture of what can be found on silicon.

Combinations of rail clamps and diodes

Since they have to absorb a lot of energy clamps, no matter how they are implemented, require a lot of area. Diodes with a forward voltage in stead of zener diodes would be much cheaper. Therefore most complex ICs have one or a few central clamps and all other pins are connected via diodes.
The metal path btween the diodes and the rail clamp must be very low resistive (in the range of one Ohm or less) and wide enough to carry several Amperes for about 100ns.



Fig. 9: Typical ESD concept of a logic IC

The ESD concept shown above shares one big rail clamp (that absorbes 60% of the ESD energy) between several I/O pins. Since the forward voltage of the diodes D11 to D52 is much lower than the hold voltage of clamp M they can be designed smaller than the central clamp. This leads to a significant area and cost reduction. The side effect of this concept is a current flow from either one of the I/Os into VDD in case VDD is not supplied while one of the I/O pins is driven from an external source.

As long as there is a current sink between VDD and VSS (this can either be the consumption of the chip or an external resistor or a voltage regulator with current sink capability) a limited DC current into one of the diodes is acceptable (meaning there is no destruction to be expected. Nevertheless the current flow can impact the performance of the chip in a negative way.)
If there is no current sink but a blocking capacitor connected between VDD and VSS (which is the typical case of most applications) charging this capacitor via one of the diodes will be fatal. When the capacitor is chargd to the trigger voltage of the grounded gate NMOS (or whatever other snap back structure is used as a clamp) the capacitor will discharge into the protection. Using snap back protctions this discharge will destroy the chip!

EMC recommendation:
If RF is applied to one of the I/O pins the RF signal will be rectified by the ESD diodes charging the supply (and the capacitor between VDD and VSS). If the RF signal pumps up VDD to the trigger voltage of the ESD protection this can lead to immediate destruction of the chip.

Summary

Literature: