Normaly integrated circuit
operate in a carefully monitored environment. This is true for most signal
processing circuits no matter if the design is digital or analog.
For power drivers and interface
circuit a protected supply is not always a given. Reverse supply may take
place.
Circuits not protected accordingly
will be destroyed by excessive power dissipation due to currents flowing
through parasitic diodes. An example of such diodes is given below:
Fig. 1: Standard CMOS circuit
with parasitic diodes.
The intentional componens
are drawn in black. The parasitic diodes are red.
Reversing the power supply
excessive current will flow through D3 and once two times the forward voltage
is exceeded even through D1 and D2.
These diodes are present
in all junction isolated process variants.
Fig. 2: Cross section of
a standard junction isolated process with P-substrate
Figure 2 illustrates where in the cross section the diodes D1 to D3 can be found.
To obtain reverse polarity protection adding a rectifier D4 is an option.
Fig. 3: Circuit protected
by diode D4
To implement the diode simply supplying the IC via a P+ contact sitting in the PMOS nwell is possible.
Fig. 4: Cross section of
the circuit including protection diode D4
The circuit shown above has
several draw backs:
1. Diode D4 has a parasitic
PNP with the P+ region being the emitter, the nwell being the base and
the substrate being the collector. This PNP creates a latch up hazard.
2. D4 lowers the supply
voltage of the IC. Logic circuits get slower. Analog circuits have less
head room for large signals.
Bypassing the diode with a MOS transistor is recommended. To do so the diode simply is replaced by M3. D4 however remains as a parasitic of M3.
Fig. 5: Bypassing the protection
diode with a PMOS to reduce the voltage drop.
This way the drop under normal operating conditions can be reduces. Latch up risk now depends on the currents applied during latch up tests and the Rdson of M3.
Fig. 6: Cross section of
the protection with PMOS bypass transistor.
Replacing the PMOS of figure
5 by an NMOS protection on the ground side offers two advantages:
1. Specific Rdson of NMOS
transistors usually is significantly lower (because electron mobility is
higher than hole mobility). This way M3 can be designed smaller.
2. The vertical PNP incorporated
in M3 of figure 5 is replaced by a lateral NPN in figure 8. The lateral
transistor usually has a lower gain than the vertical transistor of M3
of figure 5. So latch up risk is reduced.
Fig. 7: Protecting against
reverse polarity on the low side using an NMOS transistor
Fig. 8: Cross section of
a reverse supply protection with an NMOS transistor.
The dissadvantage of the circuit of figure 7 is the resistance between the substrate and the system ground. Especially in RF circuits capacitively coupled signals can lead to a significant substrate bounce. Through the substrate undesireable signals can propagate to other parts of the circuit and reach the drains of other NMOS transistors through the drain-substrate capacity.
Placing the NMOS on the supply side offers better RF performance. This approach requires a twin well process and a charge pump.
Fig. 9: Placing the nmos
on the high side
To start the circuit first
the charge pump is supplied by the diode D4. Once the chargepump is running
M3 turns on bypassing D4.
The following figure shows
a process cross section. Be aware that M3 is placed in a isolated p-well
sitting inside an nwell thus seperating it from substrate!
Fig. 10: Isolated NMOS as
an ideal high side rectifier.
References:
Circuits showing diode protections
are published in:
INTERSIL IH5040-IH5051 datasheet
(In this data sheet the bulk is described as floating. drawing a cross
section the diodes become obvious).
Circuits showing bidirectional
switches (that interrupt currents of both polarities) are published in:
Siliconics Application Note
AN77-2, Siliconics Incorporated, 1977
A circuit showing a switched
bulk to eliminate a parasitc diode is published in:
McMOS integrated circuits
data book, Motorola, 1973 page 2-29
A circuit showing an nmos
transistor as reverse polarity protection in the positive supply path is
published in:
Infineon technical information,
"Semiconductors", 2004, page 349