Fig. 1 3 bit flash ATD
For a few bits the flash converter is affordable. Assuming we want to build a 8 bit converter we will have to build 255 comparators! Even worse, the smaller the step size (LSB, least significant bit) the higher the offset requirements of the comparators. Since we want to have sufficient yield every comparator must be designed to meet a performance of about:
4 sigma < LSB
Example:
5V input swing, 8 bit leads to a LSB of 20mV. So the offset spread of one comparator should be less than 5mV. This leaves 4 sigma tolerance before the offsets of two neighboring comparators can make the thresholds touch. (Assuming that one comparator has + 4 sigma tolerance and the next one is almost perfect again.).
4 sigma tolerance leads to a yield loss of 0.04% per comparator. Using 255 comparators the total yield of the chip can not be better than 89.8%.
This calculation is already too optimistic because it might well be that there are two adjacent comparators with for example +2 sigma next to -2 sigma deviation next to each other! So the true yield (at least as long as we require monotonic code) is surely less than 89%! (Rough guess: the yield drops down to 50% or less taking the +-2 sigma cases into account too)
Better design for 6 sigma < LSB to stay profitable for 8 bit