Delta Sigma Converters (for analog
designers)
(First Published June. 2008, Update May 13 2017)
For most analog designers delta sigma converters look quite confusing
on the first glance. Therefore in this tutorial the concept of a first
order converter is developed from a pure analog system to a complete
converter.
Simulation is somewhat difficult because either a mixed signal approach
has to be chosen or all analog functions must be represented by a
digital model. Since mixed signal approaches like verilogA or VHDLA are
not yet common for open source tools here a verilog model approach will
be shown.
1st Step: The pure analog buffer
This is a simple thing Vout=Vin.
Fig. 1: Analog buffer using an OPAMP with feedback
2nd Step: Looking into the buffer
amplifier
For stability reasons the amplifier inside
the buffer must have a dominant pole. So usually it is an integrator
combined with a very high gain amplifier. So it looks like this:
Fig. 2: Analog buffer with OPAMP broken down into an integrator and a
gain stage.
Verilog Model of an Integrator:
In verilog a first draft integration
function can be implemented as a module INT8BIT.v
. The module shifts the range of 0..255 to a range of 512 to 767 to
prevent underflow or overflow during the calculation of internal
states. In the last line
assign OUT=(STATUS-OFF512);
the range is shifted back to 8 bit or 0 to 255 decimal. And here is the
test bench and it's usage.
Verilog Model with Slower Integration:
The first model is very aggressive because
a difference of the two inputs of 255 will immediatelly drive the model
into clipping. Increasing the internal nummeric range the following model will
require at least 8 clocks to go
from mid range into clipping. Integration time increases by factor 16
due to the 4 bit shift operations.
3rd Step: Changing the feedback into
an ATD and a DTA
Now we close the feedback loop using an
analog to digital (ATD) converter and a digital to analog (DTA)
converter. Still the same system (as long as the dominant pole remains
inside the integrator) except that now we have a digital output signal.
Fig. 3: An ATD with feedback
This kind of system will produce an output signal that is as close to
the original input signal as the quantisation error of the ATD allows.
Of course due to quantisation at the output the system will in most
cases have a certain error. Since the output signal is compared to the
input via the DTA and the summing point the difference between the
output signal and the input signal will be integrated and amlified. The
system will hoover around the true value such that the average signal
at the output gets very close to the input signal.
4th Step: Finding the average with a
digital filter
To get closer to the average value of the
system hoovering arround a DSP with some kind of a digital low pass
algorithme can be used. Of course inside the DSP the number of bits
used must be higher than the number of bits available at the output of
the ATD.
Fig. 4: Adding a DSP to enhance the resulution.
5th Step: Simplifying the circuit
Assuming we have enough time even a very
poor performing ATD can be averaged to achieve a reasonable resolution
the circuit shown above can be simplified dramatically. Let us simply
use 1 bit ATD (to be more clear: a simple comparator) and do the rest
by a digital low pass.
Verilog Models of the analog to
digital and digital to analog conversions
Like the integrator the comparator too can
be modeled in veriog. The model is simple: AD1.v
And to convert back into the range of the analog signal reaching from 0
to 255 we just use a 1 bit digital to analog conversion like: DA1.v
It simply converts a logic 0 into an analog 0 and a logic 1 into full
range analog of 255.
Now I already hear all the analog designers yell: That damned thing
will oscillate! So what. As long as the digital filter is clocked fast
enough (at least double the oscillation frequency) the average number
of ones and zeroes found will correspond the analog input signal. This
basically is an oscillator with a duty cycle depending on the analog
input signal. Mathematically exactly the same thing as a switchmode
power supply - and this is all we want.
Fig. 5: DS
converter without dithering
One ugly characteristic still exists. The signal is periodic. The
closer the input signal gets the limit of the input range the lower the
period gets (for intance there migt be 99 zeroes and one one per period
corresponding a 1% of full range signal). This periodic signal still is
visible behind the digital filter. This is called pattern noise.
(By the way: Since the feedback uses a resistor this is a continuous
time integrator. So this topology is named Continuous time sigma delta
converter.
If the resistor is replaced by a switched capacitor the integration
becomes time discrete. Thus the system is called discrete time delta
sigma converter.)
Checking the System with a Verilog
Model
To check the system we can use a verilog
model. It consists of the integrator, the analog to digital converter
and the digital to analog converter. The system is described by the
lines
/* make it a unity gain amplifier closing the loop */
INT16NN I1(analog, inp, daout, clk);
AD1 I3(adout, analog, clk);
DA1 I4(daout, adout, clk);
'inp' is the 8 bit wide input signal of the integrator model.
'analog' is the 8 bit wide output signal of the integrator model.
AD1 converts signal 'analog' into a one bit digital signal callde
'adout'.
DA1 closes the loop converting 'adout' back into the range of the
analog signals. 8 bit wide signal 'daout' then is fed back into the
inverting input of the integrator.
6th Step: Add Noise to dither the
pattern noise
To get rid of the pattern noise that can
be heard too well some more or less white noise can be added to the
system to break the period. Basically the energy of the pattern noise
just gets distributed over a wide frequency range.
Fig. 6: A complete first order Delta Sigma Converter.
By the way this also exists in the analog world: It corresponds a
switch mode power supply with EMC reduction using FM modulation with
noise to spread the spectrum.